The present invention relates to the field of integrated circuits. More particularly, the present invention relates to techniques for interfacing integrated circuits to external memory.
Processing systems generally include a central processing unit (CPU), logic, internal memory, and a system bus coupling the CPU, logic and internal memory. It is often necessary in processing systems to interface the system bus with external memory. The external memory may include static memory, such as flash memory, or dynamic memory such as synchronized dynamic random access memory (SDRAM).
One approach to interfacing a processor system to an external memory includes using a memory interface. In a programmable or configurable system on a chip, a memory interface having programmable input/output pins (PIO) may be used. The PIO pins of the memory interface are programmed to be used as address or data lines for the external memory. The unused address and data lines are used as user-defined PIO pins. PIO pins are expensive, however, so that it is necessary to preserve as many pins as possible for the user. If more than one external memory needs to be interfaced with a memory interface of a processor system, fewer pins are available for use by the user.
A integrated circuit is described. In one embodiment, the integrated circuit includes a processor, a bus coupled to the processor, a memory interface and an interface bus. The memory interface provides an interface between the bus and at least two memory devices including a first memory device and a second memory device. The interface bus is coupled to the first memory device, the second memory device and the memory interface. Control signals, address signals and data signals are transmitted over the interface bus.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.